Efficient post-silicon validation via segmentation of process variation envelope - Global vs local variations

In this paper, we propose an efficient method for incorporating the knowledge of global (worst case of on-die, across die, across wafers, and across wafer lots) and local (worst case on-die) process variations into a systematic framework for identifying delay marginalities in a design during first-silicon validation. With the goal of significantly reducing the number of vectors required for validation, we propose an approach for segmenting the normal process variation envelope into sub-envelopes, where each sub-envelope is guaranteed to capture worst-case local variations, and where all sub-envelopes collectively capture the worst-case global variations. We then use our recent approach for generating multiple vectors (vector-spaces) [15] in a segment-by-segment manner to guarantee the invocation of the worst-case delay of the chips in the first-silicon batch. We present extensive experimental results to demonstrate the effectiveness of our approach, especially in the context of increasing process variations.